During the clock cycle, the signals propagate through the combinatorial logic of the stage, producing an output just in time to be captured by the next pipeline latch at the end of the clock cycle.įigure 5 – A pipelined microarchitecture in more detail. In effect, the clock "pumps" instructions down the pipeline.Īt the beginning of each clock cycle, the data and control information for a partially processed instruction is held in a pipeline latch, and this information forms the inputs to the logic circuits of the next pipeline stage. A common clock signal synchronizes the latches between each stage, so that all the latches capture the results produced by the pipeline stages at the same time. The pipeline stages are separated by latches. Not bad, huh?įrom the hardware point of view, each pipeline stage consists of some combinatorial logic and possibly access to a register set and/or some form of high-speed cache memory. This is a four-fold speedup without changing the clock speed at all. Now the processor is completing 1 instruction every cycle (CPI = 1). With this scheme, a simple processor might take 4 cycles per instruction (CPI = 4).įigure 2 – The instruction flow of a pipelined processor. Instead, several instructions are all partially executing at the same time.Ĭonsider how an instruction is executed – first it is fetched, then decoded, then executed by the appropriate functional unit, and finally the result is written into place. In fact, that hasn't happened since the middle of the 1980s. Instructions are executed one after the other inside the processor, right? Well, that makes it easy to understand, but that's not really what happens. Pipelining & Instruction-Level Parallelism How can this be? Obviously, there's more to it than just clock speed – it's all about how much work gets done in each clock cycle. At the other extreme, an IBM POWER2 processor at just 135 MHz matched the 400 MHz Alpha 21164 in floating-point speed, yet was only half as fast for normal integer programs. A PowerPC G3 at that same 300 MHz was somewhat faster than the others for normal integer code, but still far slower than the top three for floating-point.
#CPU NOT POWERFUL ENOUGH PIANOTEQ 5 CODE#
A 300 MHz Pentium II was also about the same speed for many things, yet it was about half that speed for floating-point code such as scientific number crunching.
Table 1 – Processor performance circa 1997.Ī 200 MHz MIPS R10000, a 300 MHz UltraSPARC and a 400 MHz Alpha 21164 were all about the same speed at running most programs, yet they differed by a factor of two in clock speed. Look at the results for processors of a few years ago (the late 1990s). The first issue that must be cleared up is the difference between clock speed and a processor's performance. It pulls no punches and the pace is pretty fierce (really). In no time, you'll be discussing the finer points of in-order vs out-of-order, hyper-threading, multi-core and cache organization like a pro.īut be prepared – this article is brief and to-the-point.
WARNING: This article is meant to be informal and fun! Data Parallelism – SIMD Vector Instructions.Threads – SMT, Hyper-Threading & Multi-Core.Instruction Scheduling, Register Renaming & OOO.
Pipelining & Instruction-Level Parallelism.
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